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Additional info for 68HC11 Technical Docs
There is also a 192 byte mask programmed boot ROM in the MC68HC11A8. This bootstrap program ROM controls the operation of the special bootstrap operating mode and is only enabled following reset in the special bootstrap operating mode. 3 Special Bootstrap Operating Mode. 4 RAM The 256 byte internal RAM may be relocated during initialization by writing to the INIT register. The reset default position is $0000 through $00FF. This RAM is implemented with static cells and retains its contents during the WAIT and STOP modes.
MC68HC11A8 TECHNICAL DATA SERIAL PERIPHERAL INTERFACE MOTOROLA 6-5 6 WCOL — Write Collision The write collision bit is set when an attempt is made to write to the serial peripheral data register while data transfer is taking place. If CPHA is zero a transfer is said to begin when SS goes low and the transfer ends when SS goes high after eight clock cycles on SCK. When CPHA is one a transfer is said to begin the first time SCK becomes active while SS is low and the transfer ends when the SPIF flag gets set.
In output handshake, STAF is cleared by reading the PIOC register with STAF set followed by writing to the PORTCL register. STAI — Strobe A Interrupt Enable Mask When the I bit in the condition code register is clear and STAI is set, STAF (when set) will request an interrupt. CWOM — Port C Wire-OR Mode CWOM affects all eight port C pins together 0 = Port C outputs are normal CMOS outputs 1 = Port C outputs act as open-drain outputs HNDS — Handshake Mode When clear, strobe A acts as a simple input strobe to latch data into PORTCL, and strobe B acts as a simple output strobe which pulses after a write to port B.